Modern integrated circuit designs are becoming more and more complex and compact. Generally, integrated circuits encompass several electronic components such as logic gates, flip-flops, comparators, multiplexers etc. Components in an integrated circuit are interconnected using interconnections such as metal wires, which are also referred to as signal leads or signal wires. A signal wire is typically designed to transfer a signal from a component, known as driver cell, to another component, known as receiver cell or load cell. The signal, when transferred, is characterized by several parameters, particularly current density parameters such as average value, “rms” current densities (rms=root mean square), peak current densities and the like. In order to ensure that the current density parameters do not exceed corresponding pre-defined threshold values when the circuit is used later after fabrication, the current density parameters on signal leads usually are estimated during the design of an integrated circuit.
Simulation tools are known in the art which consider a digital representation of the integrated circuit. A software program for simulation of analog, digital or mixed electronic circuits well known in the art is the SPICE program (SPICE=Simulation Program with Integrated Circuit Emphasis), which is currently used for such simulations. The basic function of the interactive SPICE simulation is finding algorithmic approximate solutions for differential equations which describe the system. Their context is defined by the circuit topology and is transferred to the simulator via a net list which describes the components and their interconnections. A net is a direct interconnect between a driver cell and one or more load cells. The components can be described either by physical oriented models or can be described in a completely abstract way. In the latter case, a subsystem is then described by inputs and outputs and affiliating equations only instead of building it from single components. The simulation can employ virtual measuring devices such as amperemeters, network analyzers, logic analyzers and the like yielding measured values of parameters of the integrated circuit under analysis.
In state-of-the-art integrated circuits more devices are compressed in the integrated circuits to improve the performance. However, the currents in these devices typically remain comparable despite increasing miniaturization of the integrated circuits. With higher current density the integrated circuits become more susceptible to electromigration which causes the integrated circuit to fail.
The metallic conductors that carry current between various components on the chip are usually arranged in dense arrays. At high current densities a net atomic flux can be induced by a transfer of electron momentum to the atoms in the crystalline structure of the metallic conductors. The atomic flux results in voids which can cause a circuit the break open or in hillocks, e.g. accumulation metal leading to shorts with adjacent metal lines. A current running through a signal line may heat due to Joule heating and thus induce a temperature increase in neighboring electric lines and vice versa. In order to avoid deleterious effects occurring in the neighboring lines, the maximum temperature of signal lines should be limited.
It is desirable to determine the current density and the electromigration risk early in the design cycle as it becomes difficult to make appropriate adjustment in the design without adding considerable amount of time delays to the design cycle. Various solutions have been suggested so far for determining the current density and electromigration risks of signal nets in the integrated circuit early in the design cycle.
The U.S. Pat. No. 7,042,705 discloses a method which encompasses a driver cell modeled by triangle current pulses with properties derived from characterization of the driver cell by given formulas. A SPICE-like simulation is employed. The wiring is modeled as an impedance network.
A similar approach employing an impedance network as wiring model and SPICE-like simulation is described in the U.S. Pat. No. 6,954,914, wherein the driver cell is replaced by a simplified “appropriate” cell (e.g. inverter, buffer, etc.) of the same driving capability. As a result it can be determined if a whole net fails.
The U.S. Pat. No. 6,857,113 suggests modeling the wiring as an effective capacitance and employs a driver current ramp from timing analysis. A pre-selection of potential failures is possible. However, a detailed net simulation is necessary for verifying that the net fails.
In view of the foregoing, there is a need for revealing more details of net failures caused by electromigration, particularly determining individual failing areas in a signal wire net.